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Location : Austin, TX
Duration : Contract / Full Time
This contract position will support and develop EDA tools on the Front End RTL Design, RTL/GATE Level Simulation for CPU, GPU, Memory Controller, and Interconnect IPs.
Work between the Design/Verification teams and the vendors on the supporting the following tools: Cadence IES, Synopsys VCS, Verdi, Formal Verification, RTL Linter and Verification IPs (for AMBA AXI/ACE, DDR Protocols)
Work on EDA tool evaluations, Flow development, Deploy and Support them for Design/Verification teams.
Work on CAD/Verification infrastructure development
Help define and evolve our Design/Verification methodologies.
Desired Skills and Experience
8+ Years of Experience on Front End RTL Design/Verification/CAD role
Tools knowledge : Cadence IES, Synopsys VCS, Verdi, Formal Verification, RTL Linters and Verification IPs
Strong Perl or other UNIX scripting knowledge is preferred
Languages knowledge: Verilog, System Verilog, System Verilog Assertions (SVA)/PSL, C, C++
Protocol Knowledge for AMBA AXI/AXI4/ACE, DDR3, LPDDR2
CPU,GPU,SOC work experience is preferred
Education: BSEE MSEE preferred