Be responsible for designing and verifying sections within modu's next-generation SOCs.
Knowledge of ASIC design including architecture, verification of integrated system, RTL design, synthesis, and timing closure.
Experience with verification tools such as Specman, SystemVerilog or Vera, is an advantage.
LINT, PTSI, and Verilog are advantages.
Design experience and background in low power, high volume applications is desired.
Experience in designing communication protocols such as UART, SD, SPI, I2C is an advantage.
Experience with embedded systems, is an advantage.
Proficiency in Perl or TCL script languages desirable.
Strong written and oral communication skills.
Five years of relevant experience
BSEE in Electrical Engineering or equivalent.