Alliance Semi Jobs on Startuply

Senior Design Verification Engineer in San Jose

Thu, 23 May 2013 09:30:28 GMT

Rapid Bridge is looking to immediately hire a full-time or contract Design Verification Engineer to join our team in San Jose, California.

Senior Design Verification Engineer

Requirements:

1. Verification Engineer with good debugging skills
2. Complex verification environment for networking devices (TCP/IP)
3. Verilog HDL
4. SystemVerilog HVL
5. VCS simulation
6. Good Object-oriented programming (OOP) skills
7. VMM experience is a big plus

Interested and qualified candidates please send your resume to Javier Leon at jleon@rapidbridge.com or apply online (http://rapidbridge.catsone.com/careers/)

ABOUT US

Rapid Bridge LLC (www.rapidbridge.com) is a privately-held semiconductor technology company with a unique approach to addressing the industry's issues of cost, performance, power, and time to market. On March 22, 2010, Rapid Bridge acquired QThink, a San Diego-based, privately-held IC design services company with offices in San Jose, California and Bangalore, India. The acquisition will enable Rapid Bridge to offer its clients full front-to-back IC design services (full article http://rapidbridge.com/220310.php).

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Senior/Lead Analog IC Design Engineer (contract) in Tarrytown

Tue, 21 May 2013 20:54:37 GMT

Senior/Lead Analog IC Design Engineer (contract)

Location: Tarrytown, NY
MUST be a US Citizen or US Permanent Resident (green card holder)
Start date: 1st-2nd week in September
Duration: 5-6 months

Duties and Responsibilities:
• IC design and lead a project.

Required skills (must haves):
• Analog IC design, deep hand-on experiences in Buck/Boost DC-DC converters, PWM logic sequencing.
• Several experiences in managing the complete chip top including a test mux, etc.

Specific tool experience required:
• SpectreRF, GoldenGate, etc.
• Cadence Tools: Composer, Analog Design Environment, Spectre, Assura DRC, LVS, extranction.
• Must be fluent using Excel, PowerPoint, etc.

Experienced technologies:
• SiGe BiCMOS, CMOS < 65nm, etc.
• Dongbu HiTek BD180LV process or similar.

Education and years of experience:
• BSEE required, MSEE or higher preferred, 10 years or more.

For immediate and confidential consideration, please email your resume in Word format to Javier Leon at javierleon@cox.net

JLSG | startuply

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Senior Pixel Design Engineer in Thousand Oaks

Tue, 21 May 2013 20:54:37 GMT

Senior Pixel Design Engineer

CMOS/CCD IMAGE SENSOR GROUP on LinkedIn
Group Join Link: http://www.linkedin.com/groups?about=&gid=1696497

Summary:

The candidate must be familiar with CMOS pixel design for visible image sensors and will work closely with design engineers, the technology development department, and the silicon foundry in order to produce the highest quality pixel cells. The candidate will also plan, organize, execute, and thoroughly document his/her work, with limited supervision.

Essential:

• 3+ years of experience in CMOS pixel design or equivalent academic experience.
• Strong knowledge of pixel performance characterization and optimization.
• Strong knowledge of CMOS device physics.
• High level of discipline in producing high-quality documentation.
• Self-motivated, with a passion for imaging technologies.
• Strong verbal communication skills.

Desirable:

• Demonstrated proficiency in analog CMOS circuit design.
• Experience with CMOS-device physics simulation tools.
• Experience with back-end optical simulations, ray tracing, uLens shaping.
• Experience with CAD design tools, such as Cadence DFII and Mentor Graphics Calibre.

Education:

• BSEE required, MSEE preferred.

For immediate and confidential consideration, please email your resume in Word format to Javier Leon at javierleon@cox.net

JLSG | startuply

(key words: cmos image sensors, high definition video, imaging chip design and development)

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Senior Digital Design Engineer in Thousand Oaks

Tue, 21 May 2013 20:54:37 GMT

Senior Digital Design Engineer

CMOS/CCD IMAGE SENSOR GROUP on LinkedIn
Group Join Link: http://www.linkedin.com/groups?about=&gid=1696497

Summary:

The candidate will play a key role in the implementation of image processing algorithms, control circuits for company’s imaging products and develop interface circuits for image output and any digital circuits required in company’s products. You will also work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of Company’s products. You will design, simulate and validate digital circuits. You will also participate in synthesis, integration with third party IPs, timing closure and physical design of digital circuits. The position requires the following knowledge and experience. The candidate will also plan, organize, execute, and thoroughly document his/her work, with limited supervision.

Essential:

• 7+ years of experience in RTL design, preferably related to imaging or image processing products.
• Experience in RTL programming languages like Verilog/VHDL. Verilog experience is preferred.
• Experience with digital simulation, synthesis and timing sign-off tools.

Desirable:

• Knowledge of CMOS image sensors and image processing.
• Analog ASIC design experience.
• Hardware/FPGA design experience.
• Experience in integrating third-party IPs.

Education:
• BSEE required, MSEE preferred.

For immediate and confidential consideration, please email your resume in Word format to Javier Leon at javierleon@cox.net

JLSG | startuply

(key words: cmos image sensors, high definition video, imaging chip design and development)

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Systems and Algorithms Engineer in Thousand Oaks

Tue, 21 May 2013 20:54:37 GMT

Systems and Algorithms Engineer position

CMOS/CCD IMAGE SENSOR GROUP on LinkedIn
Group Join Link: http://www.linkedin.com/groups?about=&gid=1696497

Summary:

The candidate must be proficiency in C++/MATLAB/RTL. Solid background in mathematics. Demonstrated proficiency in circuit debug and verification. Experience of statistical data analysis using various tools like JMP/SAS. Ability to conceive and develop algorithms. Ability to work independently or as part of a team. Must be disciplined in producing clear, good quality documentation. Ability to contribute to several projects concurrently. Be a key member in a world-class team of engineers developing high-end imaging products. Assume a key role in driving future SoC architectures and image data processing algorithms employed therein. Model and systematically test new algorithms using tools such as MATLAB. Develop new evaluation tools and methods.

Desirable:

• Prior experience in imaging, in school or industry.
• Familiarity with digital cameras/camcorders.
• Experience in working closely with a semiconductor manufacturing firm.
• Digital or analog ASIC design.
• Experience working with Altera FPGAs is a plus.

Education:

• BSEE required, MSEE preferred.

For immediate and confidential consideration, please email your resume in Word format to Javier Leon at javierleon@cox.net

JLSG | startuply

(key words: cmos image sensors, high definition video, imaging chip design and development)

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Senior Analog Layout Engineer (contract) in San Jose

Tue, 21 May 2013 20:54:37 GMT

Senior Analog Layout Engineer

Locations: Tarrytown, NY or Hayward, CA
MUST be a US Citizen or US Permanent Resident (green card holder)
Start date: Immediate
Duration: 2-3 months

Required skills (must haves):
• Analog IC physical layout, layout verification tasks (DRC, LVS, ERC, density, extraction, etc.)

Specific tool experience required:
• Cadence Tools: Composer, Analog Design Environment, Spectre, Assura DRC, LVS, extraction.
• Must be fluent using Excel, PowerPoint, etc.

Experienced technologies:
• (e. g. SiGe BiCMOS, CMOS < 65nm, etc.): Dongbu HiTek BD180LV process or similar.

Education and years of experience:
• 5 years or more actual layout experiences.

For immediate and confidential consideration, please email your resume in Word format to Javier Leon at javierleon@cox.net

JLSG | startuply

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Senior Analog/Mixed-Signal IC Design Engineer in San Diego

Tue, 21 May 2013 20:54:37 GMT

Analog/Mixed-Signal IC Design Engineer

** Location: Carlsbad/San Diego, California
** MUST be a US Citizen or US Permanent Resident (green card holder)
** Full-time/Direct-hire

Our client is seeking an experienced analog/mixed-signal IC design engineer to join their ASIC design team to develop circuitry and architecture for complex custom ASICs. Job responsibilities include all aspects of ASIC development from architecture studies to tape-out activities, testing and characterization.

Requirements:

• A minimum of M.S. degree in Electrical Engineering, Ph.D. preferred.
• 6+ years of analog/mixed-signal IC design experience with track record from product conceptualization to characterization.
• Experience in submicron CMOS circuit design and layout techniques as applied to
- I/O interface circuits
- high performance data converter design (ADC, DAC)
- PLLs, crystal oscillators
- Voltage regulators, bandgap reference circuits
- High voltage protection techniques, ESD methodology

• Experience in behavioral modeling with Verilog-A, Verilog-AMS, and advanced simulation techniques, MATLAB/Simulink expertise.
• Experience with Cadence Virtuoso, layout design and verification.
• Knowledge of digital design flow, Verilog/VHDL, synthesis, place and route is a plus.

For immediate and confidential consideration, please email your resume in Word format to Javier Leon at javierleon@cox.net

JLSG | startuply

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Senior Digital ASIC Engineer in San Diego

Tue, 21 May 2013 20:54:37 GMT

Senior Digital ASIC Engineer

** Location: Carlsbad/San Diego, California
** MUST be a US Citizen or US Permanent Resident (green card holder)
** Full-time/Direct-hire

Our client is seeking an experienced Digital ASIC Engineer, responsible for designing and testing the ASIC. This includes high level RTL code optimized for foundry libraries, specifying constraints, running the tools (RTL compiler + Encounter SOC + Prime Time) and timing closure as well as simulations, both functional RTL and post layout timing. Candidate must understand the scripts and have knowledge of C programming and scripting to accomplish the tasks. Knowledge of FPGA emulation and running FPGA tools with embedded processor such as NIOS II is required. Our client is looking for expert in the Cadence ASIC tools backend and foundry libraries; successful candidate must show extensive knowledge of above areas, as much as someone who’s been working with them for 5 years or more.

Skills /Experience:

• Self-starter who can work with minimal supervision.
• Version control knowledge is mandatory.
• Thorough understanding of Cadence tools to take RTL to GDSII and running timing closure / simulations.
• C programming and scripting to support ASIC flow.
• USB3, PCI express, SATA, and other high speed serial host interface experience strongly desired.
• FPGA with embedded processor experience a plus.

Education Requirements:

• Minimum Bachelor’s degree in Computer Science, Computer Engineering or Electrical Engineering.
• Hands-on ASIC design and layout experience.

For immediate and confidential consideration, please email your resume in Word format to Javier Leon at javierleon@cox.net

JLSG | startuply

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Senior Physical Design Engineer / Applications Engineer in San Diego

Mon, 20 May 2013 18:34:26 GMT

Rapid Bridge has an immediate need to hire multiple full-time or contract Physical Design Engineers to join our team in San Diego, California.

Senior Physical Design Engineer / Applications Engineer

Duties/ Responsibilities:

• You will own one or more parts of the physical design process from Netlist to tapeout, including floorplanning, place and route, physical optimization, timing closure and/or physical verification.
• Responsibilities include core floor planning and partitioning, physical synthesis, place and route, clock tree synthesis, power and signal integrity analysis and timing closure.

Requirements/ Skills:

• Candidates must have a strong physical design background and should have prior experience in implementation of complex, high-performance, low-power design using latest industry toolsets that must include Cadence First Encounter for floorplanning, Magma Talus for P&R and Synopsys PT/PTSI for timing closure. Experience with Mentor Graphics Olympus, Apache RedHawk and Calibre is a plus.
• Technical depth in the areas of synthesis, floorplanning, place and route, timing closure and electrical analysis is a must.
• Experience with 45nm or below is required.
• Education Requirements: Bachelor's degree in Electrical Engineering required; Master's degree in Electrical Engineering preferred.

Please email me your resume in Word format to jleon@rapidbridge.com or apply online at http://www.rapidbridge.catsone.com/careers/index.php

ABOUT US

Rapid Bridge (http://www.rapidbridge.com/) has disruptive and game changing technologies and services to solve the industry’s dilemmas of cost, performance, power and time to market.

Rapid Bridge’s Design Services Division is a global leader in cutting edge integrated circuit design technology with extensive, proven experience delivering complex multi-million gate chip designs targeted to multiple deep sub-micron technologies. We are a full front-to-back design services solution utilizing our proven, propriety implementation methodologies and expertise in the latest EDA tools to get your product to market faster with first-pass silicon success. We have completed nearly 300 complex integrated circuit design projects on time and on budget. We have an enviable track record with more than 10 years in the Design Services Business, a matchless record in delivery and exceptional execution. We help our clients manage the challenges facing the semiconductor industry today by providing the right resources at the right time and cost. From design specification to GDSII or any step in between, we can add value to your design project. At Rapid Bridge Design Services, our track record with clients speaks for itself.

Rapid Bridge Technology Division focuses on the advancement and application of our core technologies. We have incorporated our patented technologies across our product families: LiquidIP™, LiquidASIC™, LiquidSoC™ and Core Power Reduction (CPR™) Technology. Our high performing metal programmable technology helps our customers go to market in the shortest time and with the least costs while maintaining COT performance.

Rapid Bridge has a worldwide presence with Design Centers in San Diego and San Jose California, Raleigh North Carolina and Bangalore India affording our clients better access to our resources. Headquartered in the San Diego Tech Center (http://www.mpgoffice.com/SanDiegoTechCenter/), this campus offers an abundance of amenities that makes it an ideal and productive location for Rapid Bridge employees!

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Senior Design Verification Engineer in San Diego

Fri, 17 May 2013 15:42:36 GMT

Rapid Bridge’s Design Services Division has an immediate need to hire full-time or contract Design Verification Engineers to join our team in San Diego, CA

Senior Design Verification Engineer

Duties and Responsibilities:

• Responsible for verifying functionality and integration of complex SoC designs, including test benches, top level and block level stimulus generation, test plans, coverage analysis, and gate level regression simulations.

Required skills (must haves):

• Experience in verification of complex SoC /ASIC’s.
• Proficient with SystemVerilog, mixed Verilog/VHDL, C++, Tcl, and Perl.
• Expertise in developing test plans, test benches, writing/debugging tests, monitors, scoreboards.
• Must be familiar with verification environments built on OVM, eRM or UVM.
• SVA is plus.
• Strong scripting and programming skills.
• Familiarity with digital logic design a plus.

Specific tool experience required:

• Cadence Incisive, Specman, eManager.

Education and years of experience:

• BS or MS with 5+ years of experience in verification of complex SoC’s.
• Experience with high speed wired communication, SONET, and OTN is a plus.

Please email me your resume in Word format to jleon@rapidbridge.com or apply online at http://www.rapidbridge.catsone.com/careers/index.php

ABOUT US

Rapid Bridge (http://www.rapidbridge.com/) has disruptive and game changing technologies and services to solve the industry’s dilemmas of cost, performance, power and time to market.

Rapid Bridge’s Design Services Division is a global leader in cutting edge integrated circuit design technology with extensive, proven experience delivering complex multi-million gate chip designs targeted to multiple deep sub-micron technologies. We are a full front-to-back design services solution utilizing our proven, propriety implementation methodologies and expertise in the latest EDA tools to get your product to market faster with first-pass silicon success. We have completed nearly 300 complex integrated circuit design projects on time and on budget. We have an enviable track record with more than 10 years in the Design Services Business, a matchless record in delivery and exceptional execution. We help our clients manage the challenges facing the semiconductor industry today by providing the right resources at the right time and cost. From design specification to GDSII or any step in between, we can add value to your design project. At Rapid Bridge Design Services, our track record with clients speaks for itself.

Rapid Bridge Technology Division focuses on the advancement and application of our core technologies. We have incorporated our patented technologies across our product families: LiquidIP™, LiquidASIC™, LiquidSoC™ and Core Power Reduction (CPR™) Technology. Our high performing metal programmable technology helps our customers go to market in the shortest time and with the least costs while maintaining COT performance.

Rapid Bridge has a worldwide presence with Design Centers in San Diego and San Jose California, Raleigh North Carolina and Bangalore India affording our clients better access to our resources. Headquartered in the San Diego Tech Center (http://www.mpgoffice.com/SanDiegoTechCenter/), this campus offers an abundance of amenities that makes it an ideal and productive location for Rapid Bridge employees!

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